1. Field of the Invention
The present invention relates to a display device which receives video signals from a computer in various modes, and displays them in accordance with the display modes; and in particular to a display device which can provide a stable display and to a display operational mode identification method.
2. Related Arts
Generally, a computer, such as a personal computer, supplies to a display device display signals, such as red, green and blue (RGB) video signals, horizontal synchronous signals and vertical synchronous signals. The display device thereafter displays predetermined images in accordance with the received display signals.
FIG. 9 is a signal waveform diagram for explaining the outline of such display signals. In FIG. 9 are shown the relationships between a video signal, a horizontal synchronous signal H.sub.S, and a vertical synchronous signal V.sub.S. The horizontal synchronous signal H.sub.S is a signal wherein a pulse signal having a pulse width H.sub.W is repeated at a predetermined cycle. A video signal is inserted between the pulses at a specified timing. H.sub.BP represents a back-porch period, and HF.sub.FP represents a front-porch period. A video signal is inserted during a period of H.sub.DSP.
The vertical synchronous signal V.sub.S is a pulse signal that is generated, in a display mode for 480 lines for example, each time the video signal is inserted between the horizontal synchronous signal, H.sub.S is transmitted 480 times for 480 lines. V.sub.W represents a pulse width, V.sub.BP represents a back-porch period, and V.sub.FP represents a front-porch period. The horizontal synchronous signal H.sub.S for 480 cycles is inserted into the display period V.sub.DSP between the back-porch period V.sub.BP and the front-porch period V.sub.FP.
A display device receiving these display signals, for example a dot-matrix display device such as a liquid crystal display panel or a plasma display panel, internally generates a timing by using the received vertical synchronous signal V.sub.S and the horizontal synchronous signal H.sub.S, obtains a video signal for each pixel by sampling the received video signal in synchronous to the timing, and drives the display panel according to the video signals. Therefore, the display device can not correctly display an image that a computer intended, so long as the display device does not recognize, as timing data, the frequency (cycle), pulse width H.sub.W, front-porch period H.sub.FP, back-porch period H.sub.BP, display signal period H.sub.DSP for the horizontal synchronous signal H.sub.S, and the frequency (cycle) and the periods V.sub.W, V.sub.FP, V.sub.BP and V.sub.DSP of the vertical synchronous signal V.sub.S.
FIG. 10 is a table showing a plurality of display modes. Display signals supplied to the display device are generated according to these display modes in accordance with the computer types. Such operational modes are, for example, the modes A through D shown in FIG. 10. Although there are various other display modes, an explanation will be given for this specification by using the above four display modes as examples.
The frequencies (cycles) of the horizontal synchronous signals H.sub.S and vertical synchronous signals V.sub.S differ in these display modes. Accordingly, the frequency of a dot clock is also different in the modes at which the display device performs sampling of a video signal for each pixel. As a result, the display periods, the front-porch periods, the back-porch periods, etc., are also different in the modes. It is, therefore, required that the display device understands exactly to which display mode the supplied display signals correspond.
However, neither a dot clock nor information concerning which operational mode is used is supplied by the computer to the display device. Thus, the display device must detect the frequency of the horizontal synchronous signal H.sub.S and/or of the vertical synchronous signal V.sub.S, and determine which display mode is being used by referring to one or both frequencies. In accordance with the determination, the display device internally generates a timing signal, such as the dot clock signal, and performs sampling of the received video signal at the timing to display a pixel for an image.
FIG. 11 is a table for explaining how the frequency of the horizontal synchronous signal H.sub.s is identified. According to the most general identification method, the intermediate value of the frequency (cycle) of each display mode is set as a reference value for identification, and the display mode is identified by determining whether the signal frequency is higher or lower than the reference value.
In other words, when the horizontal synchronous signal to be supplied has a frequency greater than the reference frequency 1, or has a cycle smaller than that of the reference frequency 1, the display mode is determined to be mode A. When the frequency of the horizontal synchronous signal is located between the reference frequencies 1 and 2, the display mode is determined to be mode B. When the frequency of the horizontal synchronous signal is positioned between reference frequencies 2 and 3, display mode is the determined to be mode C. When the frequency of the horizontal synchronous signal is lower than the reference frequency 3, the display mode is determined to be mode D.
A part of computers, however, sometimes supply a display signal with a frequency that is very far from the frequency of the mode shown in FIG. 10 or the similar frequency thereto. The worst case is when the display signal is supplied with a frequency that is near the reference frequency for identification set in FIG. 11. In this case, the identification of the display mode at a mode identification section is unstable, and each time the mode is identified, the mode may be determined as, for example, mode A or mode B. As a result, the size of a screen display is increased or reduced, or the screen is vibrated from side to side. In the worst case, a PLL circuit for generating a dot clock signal from a horizontal synchronous signal frequently goes into an unlock state and the screen display is degraded.